1. Field of the Invention
The present invention generally relates to an echo canceller and a waveform-distortion compensation device, which are applied to a line-termination unit, etc., in a digital subscriber-loop transmission.
The present invention relates, more particularly, to an echo canceller including a waveform-distortion compensation device which compensates for a distortion of an echo waveform (transmit waveform), the distortion occurring by jitter of a recovered transmit clock in a unit in which a digital phase-locked loop (DPLL) is used for timing recovery of a transmit-and-receive clock.
2. Description of the Prior Art
A description of the prior art will be given in which the echo canceller is applied to the subscriber-side line-termination unit in the digital subscriber-loop transmission.
FIG. 1 shows a configuration of a conventional line-termination unit in a subscriber facility. In FIG. 1, a transmission module 31 converts transmit data to a transmit code a1 and transmits it in an analog transmit signal form in synchronization with a transmit clock. A hybrid (HYB) circuit 32 converts the transmit signal and a receive signal between a 2-wire local line and a 4-wire subscriber facility. For example, the HYB circuit 32 transits the transmit signal from the transmission module 31 to the local line, and also transits the receive signal from the local line to a reception section. In this way, the HYB circuit 31 switches the transmit signal and the receive signal in respective directions.
In an ideal design of the HYB circuit 32, the transmit signal from the transmission module 31 is transmitted to the local line, so that the transmit signal does not affect the reception section. However, in a practical use of the HYB circuit, there is an impedance mismatch causing energy to be reflected. Therefore, a portion of the transmit signal comes around to the reception section through the HYB circuit 32 to cause an echo E.
The echo E through a HYB circuit pass is added to the receive signal from the local line, and both the echo E and the receive signal are supplied to an analog-to-digital converter (A/D converter) 33 to convert to a digital signal.
The line-termination unit includes an echo canceller 34 for canceling the echo E. In the following, operation of the echo canceller 34 will be described by referring to FIGS. 2 and 3. FIG. 2 shows an illustration for explaining a relationship between an impulse response of the echo and tap coefficients of the echo canceller. FIG. 3 shows an illustration for explaining a variation of the tap coefficient based on a change of a sampling phase. The echo canceller 34 generates an echo replica e based on the transmit code a1 from the transmission module 31. The echo canceller 34 comprises a linear echo canceller LEC for canceling a linear component of the impulse response of the echo shown in FIG. 2, and a phase compensation circuit PHC for compensating the change of the sampling phase of the echo shown in FIG. 3. The linear echo canceller LEC has tap coefficients C1, C2, . . . , C6, . . . shown in FIG. 2, and can cancel an echo response in a normal operation, i.e., no jitter of the line-termination unit.
The echo E in a received signal from the A/D converter 33 is selectively canceled by subtracting the echo replica e generated by the echo canceller 34 from the received signal at a subtraction circuit 35. A signal from which the echo was eliminated is produced as received data from a line-equalizer block 36.
A digital phase-locked loop (DPLL) circuit 37 recovers a timing based on timing information of the received data produced from the line-equalizer block 36. The DPLL circuit 37 corrects a frequency error and controls a sampling clock (receive clock) of the A/D converter 33 and the transmit clock of the transmission module 31.
FIG. 4A shows a block diagram of a configuration of the transmission module 31. FIG. 4B shows time charts for explaining an operation of the transmission module 31 shown in FIG. 4A. The transmission module 31 comprises a transmit-code converter 41, a digital-to-analog-conversion (DAC) code generator 42, a digital-to-analog (D/A) converter 43, a smoothing filter 44, and a line driver 45.
The transmit-code converter 41 converts the transmit data to the transmit code a1 (for example, a transmit code such as 2B1Q code). The DAC-code generator 42 generates a DAC code (digital data) for D/A-converting of the transmit code a1. The D/A converter 43 converts the DAC code from a digital form to an analog form. The smoothing filter 44 smoothes an analog output of the D/A converter 43. The line driver 45 transmits an output of the smoothing filter 44 to the local line as the transmit signal.
The DAC-code generator 42 is supplied with the transmit clock in synchronization with the recovered timing from the DPLL circuit 37. And, as shown in FIG. 4B, the DAC-code generator 42 generates the DAC code which rises and falls at a rising timing of the transmit clock. Therefore, a pulse width of the transmit signal is determined by a period of the transmit clock.
Next, a description will be given of a problem which occurs in the above prior echo canceller.
Since the DPLL circuit 37 is constructed with digital circuits, jitter occurs in the recovered clock due to a phase jump in a DPLL operation. In general, the jitter occurs once at a single clock of certain sequential clocks in a given period, and an occurrence of the jitter is repeated at the given period.
FIG. 5 shows an example of a DAC-code waveform when the transmit clock has jitter. When such jitter occurs in the clock (transmit clock) generated in the DPLL circuit 37, the pulse width of the transmit signal (DAC code) from the transmission module 31 changes as shown in FIG. 5. For example, when no jitter occurs in the transmit clock, the pulse width of the DAC code is shown in a solid line in FIG. 5. When the jitter occurs in a forward direction of the transmit clock, the pulse width of the DAC code is shortened as shown in a dotted line. And when the jitter occurs in a backward direction of the transmit clock, the pulse width of the DAC code is extended as shown in a one-dotted chain line.
As mentioned above, when the pulse width of the transmit signal changes, the waveform of the impulse response of the echo also changes according to the change of the pulse width. The change of the impulse response is carried out instantaneously, since only one jitter occurs in the transmit clock in the given period. Therefore, the conventional linear echo canceller, which may cancel the echo not including jitter, cannot track a coefficient update for the change of the impulse response of the echo. Thus, the linear echo canceller cannot generate a proper echo replica for the transmit signal (DAC code) which includes the jitter. As a result, at a receiving end, a portion of the echo (remaining echo .epsilon.), which was not canceled, increases.
Furthermore, the clock including the jitter from the DPLL circuit 37 changes the sampling phase in the A/D converter 33 in the receive section. Therefore, as shown in FIG. 3, the variation of the sampling phase changes the tap coefficients of the echo canceller. For example, in FIG. 3, when no jitter occurs, the tap coefficient is represented by "Cn". When the jitter having a width .DELTA. occurs in the forward direction, the corresponding tap coefficient is EQU Cn**=Cn-Pn.
When the jitter having the width .DELTA. occurs in the backward direction, the corresponding tap coefficient is EQU Cn*=Cn+Pn.
By the above change of the tap coefficient due to the variation of the sampling phase in the A/D converter 33, generation of the proper echo replica in the echo canceller 34 is interrupted. To eliminate this interruption, the echo canceller 34 usually includes the phase compensation circuit PHC for compensating the variation of the sampling phase of the echo.
On the other hand, to prevent the impulse response from being changed by the transmit signal having the jitter (namely to prevent the echo from being distorted), for example, the following method, is applicable. In the following method, the transmission module is improved so as not to distort the transmit signal (namely, so as to keep the pulse width of the transmit signal constant) for the jitter of the transmit clock generated in the DPLL operation.
FIG. 6 shows an example of the output of the DAC code in the case of applying the new method for preventing distortion in the transmit signal. In the example, one transmit code is changed by a small period of the jitter width of the transmit clock with extending to two sampling periods. A part of the changed transmit code in the latter sampling period is convolutionally multiplied with the DAC code in the next sampling period to produce it as the DAC code. When the jitter occurs in the transmit clock, the convolutionally-multiplying timing for the DAC code in the next sampling period is shifted by one jitter width in a jitter direction. In this way, when the jitter occurs in the transmit signal, though the phase of the transmit signal is changed, the waveform of the transmit signal is not distorted.
However, there is a problem that the above method, which causes no distortion in the transmit waveform when the jitter occurs in the transmit clock, requires a complex configuration of the transmission module.